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QL5020 QuickPCI Data Sheet
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33 MHz/32-bit PCI with Embedded Programmable Logic
Device Highlights
High Performance PCI Controller
* 32-bit/33 MHz PCI Target with Embedded * * * * * * * * *
Programmable Logic
* 560 Logic Cells * 250 MHz 16-bit counters and 275 MHz
Programmable Logic Zero-wait state target Write bursts and one-wait state Read bursts Programmable back-end interface to optional local processor Independent PCI bus and local bus (up to 160 MHz) clocks Fully Customizable PCI Configuration Space Reference design with driver code (Win 95/98/Win 2000/NT4.0) available PCI v2.2 compliant Supports Type 0 Configuration Cycles in Target mode 3.3 V, 5 V tolerant PCI signaling supports Universal PCI Adapter designs High performance PCI controller 3.3 V CMOS in 208-pin PQFP and 144-pin TQFP packages
datapaths * All back-end interface and glue-logic can be implemented on chip * Three 32-bit bus interfaces between the PCI Controller and the Programmable Logic
PCI Bus 33 MHz / 32 bits (data and address)
PCI Controller
High Speed Data Path
Target Controller
32-bit PCI Interface Programmable Logic
121/65 User I/O
High Speed Logic Cells
PCI Bus
Config space
Figure 1: QL5020 Block Diagram
Extendable PCI Functionality
* Support for Configuration Space from 0 x 40 to
Architecture Overview
The QL5020 device in the QuickLogic(R) QuickPCITM ESP (Embedded Standard Product) family provides a complete and customizable PCI interface solution combined with programmable logic. This device eliminates any need for the designer to worry about PCI bus compliance, yet allows for the maximum 32-bit PCI bus bandwidth (132 MBps). The programmable logic portion of the device contains 560 QuickLogic logic cells. The QL5020 device meets PCI 2.2 electrical and timing specifications and has been fully hardwaretested. This device also supports the Win'98 and PC'98 standards. The QL5020 device features 3.3 V operation with multi-volt compatible I/Os. Thus, it can easily operate in 3 V systems and is fully compatible with 3.3 V, 5 V, or Universal PCI card development.
0 x 3FF
* Multi-Function, Expanded Capabilities, and
Expansion ROM capable * Power Management, Compact PCI, Hot-Swap/Hot-Plug compatible * PCI v2.2 Power Management Specification compatible * PCI v2.2 Vital Product Data (VPD) configuration support
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QL5020 QuickPCI Data Sheet Rev. D
PCI Controller
The PCI Controller is a 32-bit/33 MHz PCI 2.2 Compliant Target Controller. It is capable to accept infinite length Write transactions at zero wait states (132 MBps). The QL5020 will not insert wait states during Write transfers as long as the logic in the programmable device can accept the data. The Target interface offers full PCI Configuration Space and flexible target addressing. Any number of 32-bit BARs may be configured, as either memory or I/O space. All required and optional PCI 2.2 Configuration Space registers can be implemented within the programmable region of the device. A reference design of a Target Configuration and Addressing module is provided. The Target Configuration Space and Address Decoding are done in the programmable logic region of the device. Since these functions are not timing critical, leaving these elements in the programmable region allows the greatest degree of flexibility to the designer. References to Configuration Space and Address Decoding blocks are included so that the design cycle can be minimized.
Configuration Space and Address Decode
The configuration space is completely customizable in the programmable region of the device. PCI address and command decoding is performed by logic in the programmable section of the device. This allows support for any size of memory or I/O space for back-end logic. It also allows the user to implement any subset of PCI commands supported by the QL5020. QuickLogic provides a reference Address Register/Counter and Command Decode block.
Internal PCI Interface
Figure 2 shows the interface symbol you will use in your schematic design to attach the local interface programmable logic design to the PCI core. If you were designing with a top-level Verilog(R) or VHDL file, then you would use a structural instantiation of this PCIT32N block, instead of a graphical symbol.
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QL5020 QuickPCI Data Sheet Rev. D
PCIT32N
Figure 2: PCI Interface Symbol
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QL5020 QuickPCI Data Sheet Rev. D
PCI Target Interface
Table 1: PCI Target Interface Signals Signal I/O Description
Usr_Addr_WrData [31:0]
Target address and data from target Writes. During all target accesses, the address will be presented on Usr_Addr_WrData[31:0] and simultaneously, O Usr_Adr_Valid will be active. During target Write transactions, this port will present write data to the PCI configuration space or user logic. PCI command and byte enables. During target accesses, the PCI command will be presented on Usr_CBE[3:0] and simultaneously, Usr_Adr_Valid will be active. During O target Read or Write transactions, this port will present active-low byte-enables to the PCI configuration space or user logic. Indicates the beginning of a PCI transaction, and that a target address is valid on Usr_Addr_WrData[31:0] and the PCI command is valid on Usr_CBE[3:0]. When this signal is active, the target address must be latched and decoded to determine if this O address belongs to the device's memory space. Also, the PCI command must be decoded to determine the type of PCI transaction. On subsequent clocks of a target access, this signal will be low, indicating that data (not an address) is present on Usr_Addr_WrData[31:0]. Indicates that the target address should be incremented, because the previous data transfer was completed. During burst target accesses, the target address is only O presented to the back-end logic at the beginning of the transaction (when Usr_Adr_Valid is active), and must therefore be latched and incremented by four for subsequent data transfers. O This signal will be active for the duration of a target Write transaction, and may be used by back-end logic to turn on output-enables for transmitting the data off-chip. Active when a user Read command has been decoded from the Usr_CBE[3:0] bus. This command may be mapped from any of the PCI Read commands, such as Memory Read, Memory Read Line, Memory Read Multiple, I/O Read, etc. Active when a user Write command has been decoded from the Usr_CBE[3:0] bus. This command may be mapped from any of the PCI Write commands, such as Memory Write or I/O Write. The address on Usr_Addr_WrData[31:0] has been decoded and determined to be within the address space of the device. Usr_Addr_WrData[31:0] must be compared to each of the valid Base Address Registers in the PCI configuration space. Also, this signal must be gated by the Memory Access Enable or I/O Access Enable registers in the PCI configuration space (Command Register bits 1 or 0 at offset 04h).
Usr_CBE[3:0]
Usr_Adr_Valid
Usr_Adr_Inc
Usr_WrReq
Usr_RdDecode
I
Usr_WrDecode
I
Usr_Select
I
Usr_Write Cfg_Write Cfg_RdData[31:0] Usr_RdData[31:0]
O Write enable for data on Usr_Addr_WrData[31:0] during PCI writes. O I I Write enable for data on Usr_Addr_WrData[31:0] during PCI configuration Write transactions. Data from the PCI configuration registers, required to be presented during PCI configuration reads. Data from the back-end user logic (and/or DMA configuration registers), required to be presented during PCI reads.
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QL5020 QuickPCI Data Sheet Rev. D Table 1: PCI Target Interface Signals (Continued) Signal Cfg_CmdReg8 I Cfg_CmdReg6 Cfg_PERR_Det O Parity error detected on the PCI bus. When this signal is active, bit 15 of the Status Register must be set in the PCI configuration space (offset 04h). Bits 6 and 8 from the Command Register in the PCI configuration space (offset 04h). I/O Description
Cfg_SERR_Sig Usr_TRDYN Usr_STOPN Usr_Devsel Usr_Last_Cycle_D1 Usr_Rdy Usr_Stop
System error asserted on the PCI bus. When this signal is active, the Signalled O System Error bit, bit 14 of the Status Register, must be set in the PCI configuration space (offset 04h). O Copy of the TRDYN signal as driven by the PCI target interface. O Copy of the STOPN signal as driven by the PCI target interface. O Inverted copy of the DEVSELN signal as driven by the PCI target interface. O Last transfer in a PCI transaction is occurring. I I Used to delay (add wait states to) a PCI transaction when the back end needs additional time. Subject to PCI latency restrictions. Used to prematurely stop a PCI target access on the next PCI clock.
PCI Internal Signals
Table 2: PCI Internal Signals Signal PCI_clock PCI_reset PCI_IRDYN_D1 PCI_FRAMEN_D1 PCI_DEVSELN_D1 PCI_TRDYN_D1 PCI_STOPN_D1 PCI_IDSEL_D1 I/O O PCI clock. O PCI reset signal. O Copy of the IRDYN signal from the PCI bus, delayed by one clock. O Copy of the FRAMEN signal from the PCI bus, delayed by one clock. O Copy of the DEVSELN signal from the PCI bus, delayed by one clock. O Copy of the TRDYN signal from the PCI bus, delayed by one clock. O Copy of the STOPN signal from the PCI bus, delayed by one clock. O Copy of the IDSEL signal from the PCI bus, delayed by one clock. Description
JTAG Support
JTAG pins support IEEE standard 1149.1a to provide boundary scan capability for the QL5020 device. Six pins are dedicated to JTAG and programming functions on each QL5020 device, and are unavailable for general design input and output signals. TDI, TDO, TCK, TMS, and TRSTB are JTAG pins. A sixth pin, STM, is used only for programming.
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QL5020 QuickPCI Data Sheet Rev. D
Development Tool Support
Software support for the QL5020 device is available through the QuickWorks development package. This turnkey PC-based QuickWorks package, shown in Figure 3, provides a complete ESP software solution with design entry, logic synthesis, place and route, and simulation. QuickWorks includes VHDL, Verilog(R), schematic, and mixed-mode entry with fast and efficient logic synthesis provided by the integrated Synplicity Synplify Lite tool, specially tuned to take advantage of the QL5020 architecture. QuickWorks also provides functional and timing simulation for guaranteed timing and source-level debugging. The UNIX-based QuickTools and PC-based QuickWorks and provide a solution for designers who use schematic-only design flow third-party tools for design entry, synthesis, or simulation. QuickTools and QuickWorks read EDIF netlists and provide support for all QuickLogic devices. QuickTools and QuickWorks also support a wide range of third-party modeling and simulation tools.
QuickWorksDesign Software
Third Party Design Entry & Synthesis SCS Tools Mixed-Mode Design
Schematic Verilog
VHDL/
Turbo HDL Editor
Synplify-Lite HDL Synthesis Simulator Third Party Simulation Optimize, Place, Route Silos III Aldec
Figure 3: QuickWorks Tool Suite
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QL5020 QuickPCI Data Sheet Rev. D
Electrical Specifications
AC Characteristics at VCC = 3.3 V, TA = 25C (K = 1.00)
To calculate delays, multiply the appropriate K factor from Table 9 by the numbers provided in Table 3 through Table 7.
Table 3: Logic Cells Symbol Parameter 1 tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Combinatorial Delay Setup Time Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width
b b
Propagation Delays (ns) Fanouta 2 1.7 1.7 0.0 1.0 1.2 1.2 1.3 1.1 1.9 1.8 3 1.9 1.7 0.0 1.2 1.2 1.2 1.5 1.3 1.9 1.8 4 2.2 1.7 0.0 1.5 1.2 1.2 1.8 1.6 1.9 1.8 8 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8
1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature settings as specified in Table 9. b. These limits are derived from a representative selection of the slowest paths through the QL5020 3 logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
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QL5020 QuickPCI Data Sheet Rev. D
Table 4: Input-Only/Clock Cells Symbol Parameter 1 tIN tINI tISU tIH tlCLK tlRST tlESU tlEH High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1.5 1.6 3.1 0.0 0.7 0.6 2.3 0.0 Propagation Delays (ns) Fanout a 2 1.6 1.7 3.1 0.0 0.8 0.7 2.3 0.0 3 1.8 1.9 3.1 0.0 1.0 0.9 2.3 0.0 4 1.9 2.0 3.1 0.0 1.1 1.0 2.3 0.0 8 2.4 2.5 3.1 0.0 1.6 1.5 2.3 0.0 12 2.9 3.0 3.1 0.0 2.1 2.0 2.3 0.0 24 4.4 4.5 3.1 0.0 3.6 3.5 2.3 0.0
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature settings as specified in Table 9. Table 5: Clock Cells Symbol Parameter Propagation Delays (ns) Loads per Half Column a 1 tACK tGCKP tGCKB Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay 1.2 0.7 0.8 2 1.2 0.7 0.8 3 1.3 0.7 0.9 4 1.3 0.7 0.9 8 1.5 0.7 1.1 10 1.6 0.7 1.2 11 1.7 0.7 1.3
a. The array distributed networks consist of 28 half columns and the global distributed networks consist of 32 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to eight loads per half column. The global clock has up to 11 loads per half column.
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QL5020 QuickPCI Data Sheet Rev. D
Table 6: Input-Only I/O Cells Symbol Parameter Propagation Delays (ns) Fanout a 1 tI/O tISU tIH tlOCLK tlORST tlESU tlEH Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register clock Enable Set-Up Time Input Register Clock Enable Hold Time 1.3 3.1 0.0 0.7 0.6 2.3 0.0 2 1.6 3.1 0.0 1.0 0.9 2.3 0.0 3 1.8 3.1 0.0 1.2 1.1 2.3 0.0 4 2.1 3.1 0.0 1.5 1.4 2.3 0.0 8 3.1 3.1 0.0 2.5 2.4 2.3 0.0 10 3.6 3.1 0.0 3.0 2.9 2.3 0.0
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature settings as specified in Table 9. Table 7: Output-Only I/O Cells Symbol Parameter 30 tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-State Output Delay Low to Tri-State
a
Propagation Delays (ns) Output Load Capacitance (pF) 50 2.5 2.6 1.7 2.0 75 3.1 3.2 2.2 2.6 100 3.6 3.7 2.8 3.1 150 4.7 4.8 3.9 4.2 -
2.1 2.2 1.2 1.6 2.0 1.2
a. The following loads presented in Figure 4 are used for tPXZ:
tPHZ 1 5 pF
1 tPLZ 5 pF
Figure 4: Loads used for tPXZ
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QL5020 QuickPCI Data Sheet Rev. D
DC Characteristics
The DC specifications are provided in Table 8 through Table 10.
Table 8: Absolute Maximum Ratings Parameter VCC Voltage VCCIO Voltage Input Voltage Latch-up Immunity Value -0.5 V to 4.6 V -0.5 V to 7.0 V -0.5 V to VCCIO +0.5 V 200 mA Parameter DC Input Current ESD Pad Protection Storage Temperature Lead Temperature Value 20 mA 2000 V -65C to +150C 300C
Table 9: Operating Range Symbol Parameter Industrial Min VCC VCCIO TA K Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Delay Factor -33B Speed Grade 3.0 3.0 -40 0.43 Max 3.6 5.5 85 0.9 Commercial Min 3.0 3.0 0 0.46 Max 3.6 5.25 70 0.88 V V C n/a Unit
Table 10: DC Characteristics Symbol VIH VIL VOH Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage IOH = -12 mA IOH = -500 A IOL = 16 mA IOL = 1.5 mA VI = VCCIO or GND VI = VCCIO or GND -10 -10 Conditions Min 0.5 VCC -0.5 2.4 0.9 VCC 0.45 0.1 VCC 10 10 10 VO = GND VO = VCC VI, VIO = VCCIO or GND -15 40 0.50 (typ) 0 -180 210 2 100 Max VCCIO + 0.5 0.3 VCC Units V V V V V V A A pF mA mA mA A
VOL II IOZ CI IOS ICC ICCIO
Output LOW Voltage I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitancea Output Short Circuit Currentb Quiescent Current
c
Quiescent Current on VCCIO
a. Capacitance is sample tested only. Clock pins are 12 pF maximum. b. Only one output at a time. Duration should not exceed 30 seconds. c. For -33B commercial grade devices only. Maximum Icc is 3 mA for industrial grade devices.
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QL5020 QuickPCI Data Sheet Rev. D
Kv and Kt Graphs
Voltage Factor vs. Supply Voltage
1.1000 1.0800 1.0600 1.0400
Kv
1.0200 1.0000 0.9800 0.9600 0.9400 0.9200 3 3.1 3.2 3.3 3.4 3.5 3.6
Supply Voltage (V)
Figure 5: Voltage Factor vs. Supply Voltage
Temperature Factor vs. Operating Temperature
1.15 1.10 1.05 1.00 0.95 0.90 0.85 -60 -40 -20 0 20 40 60 80
Kt
Junction Temperature C
Figure 6: Temperature Factor vs. Operating Temperature
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QL5020 QuickPCI Data Sheet Rev. D
Pin Descriptions
Table 11: Pin Descriptions Pin TDI TRSTB TMS TCK TDO STM I/ACLK I/GCLK I I/O VCC VCCIO GND Function Test Data In for JTAG Active low Reset for JTAG Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG Special Test Mode Description Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold LOW during normal operation. Connect to ground if not used for JTAG. Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG. Output that must be left unconnected if not used for JTAG. Must be grounded during normal operation.
High-drive input and/or array Can be configured as either or both. network driver High-drive input and/or global Can be configured as either or both. network driver High-drive input Input/Output pin Power supply pin Input voltage tolerance pin Ground pin Use for input signals with high fanout. Can be configured as an input and/or output. Connect to 3.3 V supply. Connect to 5.0 V supply if 5 V input tolerance is required, otherwise connect to 3.3 V supply. Connect to ground.
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QL5020 QuickPCI Data Sheet Rev. D
QL5020 External Device Pins
The definitions for the QL5020 PCI pin types are indicated in Table 12. The names of all QL5020 device pins are indicated in Table 13 and Table 14. These are pins on the device, some of which connect to the PCI bus, and others that are programmable as user I/O.
Table 12: QL5020 External Device Pins Type IN OUT T/S Input. A standard input-only signal Totem pole output. A standard active output driver Tri-state. A bi-directional, tri-state input/output pin Sustained Tri-state. An active low tri-state signal driven by one PCI agent at a time. It must be driven high for at least one clock before being disabled (set to Hi-Z). A pull-up needs to be provided by the PCI system central resource to sustain the inactive state once the active driver has released the signal. Open Drain. Allows multiple devices to share this pin as a wired-or. Description
S/T/S
O/D
Table 13: QL5020 External Device Pins Pin/Bus Name Type VCC VCCIO GND I/O GLCK/I ACLK/I TDI/RSI* TDO/RCO* TCK TMS TRSTB/RRO* STM IN IN IN Supply pin. Tie to 3.3 V supply. Supply pin for I/O. Set to 3.3 V for 3.3 V I/O, 5 V for 5.0 V compliant I/O Ground pin. Tie to GND on the PCB. Function
T/S Programmable Input/Output/Tri-State/Bi-directional Pin. IN IN IN OUT IN IN IN IN Programmable Global Network or Input-only pin. Tie to VCC or GND if unused. Programmable Array Network or Input-only pin. Tie to VCC or GND if unused. JTAG Data In/Ram Init. Serial Data In. Tie to VCC if unused. Connect to Serial EPROM data for RAM init. JTAG Data Out/Ram Init Clock. Leave unconnected if unused. Connect to Serial EPROM clock for RAM init. JTAG Clock. Tie to GND if unused. JTAG Test Mode Select. Tie to VCC if unused. JTAG Reset/RAM Init. Reset Out. Tie to GND if unused. Connect to Serial EPROM reset for RAM init. QuickLogic Reserved pin. Tie to GND on the PCB.
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QL5020 QuickPCI Data Sheet Rev. D Table 14: QL5020 External Device Pins Pin/Bus Name AD[31:0] CBEN[3:0] PAR FRAMEN DEVSELN CLK RSTN PERRN SERRN IDSEL IRDYN TRDYN STOPN Type T/S T/S T/S S/T/S Function PCI Address and Data 32 bit multiplexed address/data bus. PCI Bus Command and Byte Enables Multiplexed bus which contains byte enables for AD[31:0] or the Bus Command during the address phase of a PCI transaction. PCI Parity Even Parity across AD[31:0] and C/BEN[3:0] busses. Driven one clock after address or data phases. The Target drives PAR on PCI reads. PCI Cycle Frame Driven active by current PCI Master during a PCI transaction. Driven low to indicate the address cycle, driven high at the end of the transaction.
S/T/S PCI Device Select Driven by a Target that has decoded a valid base address. IN IN S/T/S O/D IN S/T/S S/T/S PCI System Clock Input PCI System Reset Input PCI Data Parity Error Driven active by the initiator or target two clock cycles after a data parity error is detected on the AD and C/BEN busses. PCI System Error Driven active when an address cycle parity error, data parity error during a special cycle, or other catastrophic error is detected. PCI Initialization Device Select Use to select a specific PCI Agent during System Initialization. PCI Initiator Ready Indicates the Initiator's ability to complete a read or write transaction. Data transfer occurs only on clock cycles where both IRDYN and TRDYN are active. PCI Target Ready Indicates the Target's ability to complete a read or write transaction. Data transfer occurs only on clock cycles where both IRDYN and TRDYN are active.
S/T/S PCI Stop Used by a PCI Target to end a burst transaction.
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QL5020 QuickPCI Data Sheet Rev. D
144 TQFP Pinout Diagram
PIN #109 PIN #1
QuickPCI QL5020-33BPF144C
PIN #37 Figure 7: 144 TQFP Pinout Diagram
PIN #73
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QL5020 QuickPCI Data Sheet Rev. D
144 TQFP Pinout Table
Table 15: 144 TQFP Pinout Table
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Function
I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I ACLK/I VCC RSTN CLK VCC I/O AD[31] AD[30] AD[29] AD[28] AD[27] AD[26] GND AD[25] AD[24] CBEN[3] IDSEL AD[23] AD[22]
Pin
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Function
AD[21] TDI/RSI AD[20] AD[19] AD[18] VCC AD[17] AD[16] CBEN[2] FRAMEN IRDYN TRDYN DEVSELN GND STOPN PERRN SERRN GND PAR CBEN[1] AD[15] VCCIO AD[14] AD[13] AD[12] AD[11] AD[10] AD[9] AD[8] GND CBEN[0] AD[7] AD[6] AD[5] TRSTB/RRO TMS
Pin
73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
Function
AD[4] AD[3] AD[2] AD[1] AD[0] I/O VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I ACLK/I VCC I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O
Pin
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Function
TCK STM I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O GND I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O TDO/RCO I/O
Summary: 47 PCI pins, 65 user I/O, 3 CLK/I, and 3 I.
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QL5020 QuickPCI Data Sheet Rev. D
208 PQFP Pinout Diagram
PIN #157 PIN #1
QuickPCI QL5020-33BPQ208C
PIN #53 Figure 8: 208 PQFP Pinout Diagram
PIN #105
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QL5020 QuickPCI Data Sheet Rev. D
208 PQFP Pinout Diagram
Table 16: 208 PQFP Pin Table
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Function
I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O RSTN ACLK/I VCC I CLK VCC I/O I/O AD[31] AD[30] AD[29] AD[28]
Pin
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Function
AD[27] AD[26] AD[25] AD[24] VCC CBEN[3] GND IDSEL AD[23] AD[22] AD[21] AD[20] AD[19] AD[18] AD[17] AD[16] CBEN[2] TDI FRAMEN IRDYN TRDYN DEVSELN GND STOPN VCC I/O I/O PERRN I/O SERRN PAR CBEN[1] AD[15] AD[14] AD[13] AD[12]
Pin
73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
Function
GND AD[11] AD[10] AD[9] AD[8] GND CBEN[0] AD[7] AD[6] AD[5] VCCIO AD[4] AD[3] AD[2] AD[1] AD[0] I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TRSTB TMS I/O I/O I/O I/O
Pin
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Function
I/O I/O I/O I/O I/O VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I ACLK/I VCC I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Pin
145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
Function
VCC I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK STM I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O
Pin
181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
Function
I/O GND I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O VCC I/O I/O I/O I/O I/O TDO I/O
Summary: 47 PCI pins, 121 user I/O, 3 CLK/I, and 3 I.
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(c) 2003 QuickLogic Corporation
QL5020 QuickPCI Data Sheet Rev. D
Ordering Information
QL 5020 -33B PF144 C QuickLogic device Operating Range C = Commercial I = Industrial Package Code PF144 = 144-pin TQFP PQ208 = 208-pin PQFP
QuickPCI device part number Speed Grade 33B=33 MHz standard PCI
Note: PCI bus runs with up to 50 MHz for embeded applications
Revision History
Revision A B C Date November 2002 May 2003 July 2003 Comments Preliminary release Bernhard Andretzky and Kathleen Murchek David Shih and Kathleen Murchek Added Pin Description table and updated summary for pinout tables. Bernhard Andretzky, David Hrabal and Kathleen Murchek Updated chip speed grade in illustration and part number in ordering information. Updated Figure 1. QL5020 Block Diagram, Table 9. Operating Range and Table 10. DC Characteristics. Deleted QuickWorksLite information in Development Tool Support section. Updated trademark information.
D
September 2003
(c) 2003 QuickLogic Corporation
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QL5020 QuickPCI Data Sheet Rev. D
Contact Information
Telephone: (408) 990 4000 (US) (416) 497 8884 (Canada) +(44) 1932 57 9011 (Rest of Europe) +(49) 89 930 86 170 (Germany & Benelux) +(8621) 2890 3029 (Asia) +(81) 45 470 5525 (Japan) E-mail: Support: Web site: info@quicklogic.com http://www.quicklogic.com/support http://www.quicklogic.com/
Copyright and Trademark Information
Copyright (c) 2003 QuickLogic Corporation. All Rights Reserved. The information contained in this document and the accompanying software programs is protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic and the QuickLogic logo, pASIC, ViaLink, DeskFab, QuickRAM, QuickPCI and QuickWorks are registered trademarks of QuickLogic Corporation; Eclipse, EclipsePlus, Eclipse II, QuickDR, QuickTools, QuickCore, QuickPro, SpDE, WebASIC, and WebESP are trademarks of QuickLogic Corporation.
20 * www.quicklogic.com *
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(c) 2003 QuickLogic Corporation
QL5020 QuickPCI Data Sheet Rev. D
(c) 2003 QuickLogic Corporation
www.quicklogic.com * *
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